Re: [oc] VHDL help.

Hi,

From my understanding of VHDL, these are really only used in simulation. In actual hardware, 'L', H, and X are pretty undesireable signals. Plus I do not think that there is an FPGA or CPLD out there that can implement an L or H. You can make an X but its not really recommended :)

Michael Ayton

----- Original Message -----

From: Paul McFeeters

To: cores@opencores.org

Sent: Saturday, December 08, 2001 5:29 PM

Subject: RE: [oc] VHDL help.

Kausar,

as far as I understand the function it works it way through every bit in 'arg' and changes them to 'L', 'H' or 'Z' impedance according to their previous states. I presume from the code that they don't want any signals being 'forced' to 1 or 0. Presumably this would be used in a design where forcing a 0 or 1 would cause too much current to flow, maybe a low power/battery powered device would use this method to save power?

1 = Force a 1

0 = Force a 0

L = Weak Logical 0 (high resistance/impedance)

H = Weak Logical 1 (high resistance/impedance)

Z = High Impedance (also known as tristating which is usually used so other devices can drive the same wires off chip)

Hope it helps

Paul McFeeters

-----Original Message-----
From: owner-cores@opencores.org [mailto:owner-cores@opencores.org]On Behalf Of Kausar Ahmed R
Sent: 08 December 2001 16:04
To: cores@opencores.org
Subject: [oc] VHDL help.

Hello,

   Can anyone please tell me in detail ( & in simple terms ) what exactly the following VHDL functions do ?

Also, are they supported for synthesis, especially in Xilinx Foundation-F3.1i tool ?

Thanks in advance.

   Kausar. [ kausarahmedr@yahoo.com ]

[1] FUNCTION to_high_imped(arg : bvec) RETURN bvec IS
          VARIABLE result : bvec;
      BEGIN
           FOR k in arg'RANGE LOOP
             CASE arg(k) IS
                  WHEN '0' => result(k) := 'L';
                  WHEN '1' => result(k) := 'H';
                  WHEN 'L' => result(k) := 'L';
                  WHEN 'H' => result(k) := 'H';
              !     WHEN OTHERS => result(k) := 'Z';
           END CASE;
        END LOOP;
        RETURN(result);
   END FUNCTION to_high_imped;

---------------------------------------------------------------

   And the

[2] FUNCTION To_X01 ( s : std_logic_vector ) RETURN std_logic_vector ;

( ieee, std_logic_1164 )

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