Re: [oc] Re: Opencores Design Guidelines

["Damjan Lampret" <lampret@opencores.org>]

Rudi,

is this ok:

>>
Strong Recommendation: Signals that cross different clock domains
should be sampled twice in destination clock domains (double sampling is
a MUST). See synchronizer_flop in OpenCores CVS in module common.

Prevents meta-stability state.

To make netlist verification easier, you should use one module (i.e. sync.v,
sync.vhd) that will have in, out and clock interface and the first flip-flop
should
have a unique name as this flip-flop will have timing violation. If it has
unique
name, it is easier to trace it and "change" it to not pass X's.

Also it should be clear that you pass ONLY the control signal and not the
data
bus etc.
<<

For the record, I did not write 3.3.1. If above is not ok, send me a text
that you want to see as 3.3.1. The only thing I ask to refer to synchronizer
flop in the CVS.

regards,
Damjan

----- Original Message -----
From: "Rudolf Usselmann" <rudi@asics.ws>
To: <cores@opencores.org>
Sent: Sunday, November 11, 2001 2:18 AM
Subject: Re: [oc] Re: Opencores Design Guidelines


> On Sunday 11 November 2001 02:32, you wrote:
> > Hi Richard,
> >
> > I'm very sorry but I have never received any email from you. If I would,
> > I'd reply for sure and include your suggestions and corrections. Can you
> > please send me your email again. Thanks.
> >
> > regards,
> > Damjan
>
>
> I know you received my email, but you didn't bother to fix those
> things either ...
>
> (see section 3.3.1 for a major WRONG/BOGUS recommendation !)
>
>
> Cheers,
> rudi
> --
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