[oc] VHDL on Xilinx tool

["hendra gunawan" <hendrag01@hotmail.com>]

>From: sandeep shastri <sandeep_shastri@yahoo.com>
>Reply-To: cores@opencores.org
>To: cores@opencores.org
>Date: Wed, 5 Sep 2001 07:42:20 -0700 (PDT)
>
>Dear Sir,
>As I am working on Image compression using VHDL
>on Xilinx tool and supposing you might have an
>idea about Xilinx, I have some doubts, which if
>you can solve will make it  possible for me to go
>ahead.
>1)I am getting much warnings while
>synthesis.Whether it affects the design.
what kinds of warning messages did you have? if the warning wasn't too 
serious, i think your design will go through.  but if the message warning 
are serious, example :
- signal A may have more than one driver
- cannot link to other module
i think the implementation will fail with errors.
why didn't you do simulation after synthesis? it will make sure about your 
design. and then you have to run implementation, if it passes the 
implementation, then you run the verification to make sure your design 
works.

>2)Is there any criteria about programing in VHDL
>by taking into consideration the archiecture of
>FPGA.
as long as you use general VHDL (not specialize from a company which doesn't 
support by XIlinx), i think there's no important consideration to make it 
works.  if you don't mind, may i know what software do you use to simulate 
your VHDL design?

>3)Can we get the signals defined  in the program
>to be viewed while simulation.
off course

>4) How to overcome the simulation difficulties
>while timing simulation.
i think you should use timing constraints

>        If you help me in this regard i will be
>obliged.
>              thanks

have a nice day'

Hendra

_________________________________________________________________
Get your FREE download of MSN Explorer at http://explorer.msn.com/intl.asp

--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml