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[oc] wishbone bus anad FIFO interface

To: cores@opencores.org
Subject: [oc] wishbone bus anad FIFO interface
From: Jamil Khatib <jamilkhatib75@yahoo.com>
Date: Thu, 11 Jan 2001 01:55:39 -0800 (PST)
Reply-To: cores@opencores.org
Sender: owner-cores@opencores.org

Does any one has a suggestion on connecting Wishbon
bus to FIFO buffer?

I have a proposal of such interface in the HDLC core
description, do you think it is fine?

Thanks
Jamil Khatib


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