[oc] OCRP1-board: wrong clk for sdram?

["Andreas Pachl (r8744c)" <r8744c@email.sps.mot.com>]

Hi,
I found a potential problem about the OCRP1 board:

On sheet1/page4 the sdram is clocked by CLKOUT. But this clock is also
the input for GCK2 (sheet 1/page 2).
In my opinion this is wrong. As described in the XAPP134 (Synthesizable
High Performance SDRAM Controller, p 9) the GCK2 is an input for the
clock.
Then you need 2 DLLs, one for the sdram-controller in the Xilinx and one
for the sdram. The clock for the sdram is generated  in the Xilinx with
the DLL
and then is sent to the sdram. A feedback for the DLL is sent to a
special DLL pin. In this scenario there are different clocks for GCK2
input and the sdram.

Andreas Pachl