[oc] From a new member

[Ganesh Venkataraman <gxv@cypress.com>]

I am a fresh graduate of Electronics Engineering from the Birla
Institute of Technology and Sceince (BITS), Pilani, India. I am
interested in IC Design. I am quite familiar with Verilog and RTL
design.  So far, I have designed and implemented a 16550 compatible UART

and a simple 16-bit microprocessor. If there is a need for designing
some simple cores, I could do it. That would also help me in mastering
RTL design, coding techniques and hence contribute to my learning
process.

Ganesh Venkataraman
begin:vcard 
n:Venkataraman;Ganesh
tel;home:90-080-5272995
tel;work:90-080-3530132 extn 150
x-mozilla-html:FALSE
org:Cypress Semiconductor Technology India Limited;DCD
version:2.1
email;internet:gxv@cypress.com
title:Design Engineer
adr;quoted-printable:;;137, 15th 'B' Cross,=0D=0AEashwara Layout,=0D=0AIndira Nagar Second Stage.	;Bangalore;Karnataka;;India
x-mozilla-cpt:;-19280
fn:Ganesh Venkataraman
end:vcard