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[oc] Re: ATM Core
Now I know why I didn't get any email ! All the discussions
happen on the mailing list - Dhu ! ;*)
OK, ATM core local i/f: I feel PCI would be a bad choice. I'm
looking at the PHY interface (Utopia 3) it can do about 3.2Gb/s
tops, 800Mb/s min. So that leaves out PCI, as it would not be
able to provide sufficient bandwidth.
I'll take a look at that other thing that has been suggested, and
see if that will work.
PHY i/f: Hmm, Someone suggested doing Utopia 1 and 2, and later 3.
I'm more inclined starting with 3, maybe include backwards compatibility
to 1 and 2. For Utopia 3, I would also probably not support the multi
phy feature (don't quite understand how it works yet anyway ...).
However I would probably make it configurable to support all 3 operational
modes of Utopia 3: 0.8, 1.6 and 3.2 Gb/s.
Utopia 4 is about to be released, so I'm thinking 1 & 2 will be history
anyway ...
OK a few questions:
1.1) Utopia 3 without MPHY support will be OK (for first version) ?
1.2) PHY config interface will not be included, OK ?
1.3) Supporting 0.8, 1.6 and 3.2 Gb/s: should I make the core
to be configurable at the synthesis level (e.g. parameterize it)
or should it be build in so the user/system (once in a chip) can
decide ?
2.1) Should I include the Frame assembly/disassembly logic, or should
that be in a different project ?
2.2) If yes to 2.1: Should we include multiple data DAM channels ?
e.g. we can have multiple DMAs going on at the same time, interleaving
cells ... this will be interesting, need to account for QoS as well then.
3.1) Again, I'm assuming yes to 2.1: I'm thinking of doing DMA descriptor
lists that include the link (path/channel) info and a pointer to the actual
frame data (and it's length). (Kind of a linked list in memory... ) Does
this sound OK ?
3.2) How do we handle establishing path & channels ? Do it in hardware
(how?) or leave that to SW ?
3.3) I think we might need at least one additional DMA, so we can insert
control/management cells, any ideas ?
Thanks,
rudi