Project Name: USB 2.0 Function Core

(See change Log at bottom of page for changes/updates)

 

Description

This is a USB 2.0 compliant core. USB 2.0 allows data transfers of 480 Mb/s. Because of the high interface speed, an external PHY will be required with this core. A industry standard PHY interface for USB has been developed. This interface is called USB Transceiver Macrocell Interface or UTMI for short. The host interface of the USB core will be WISHBONE SoC compliant.

More information about the USB standard and a full specification can be found at www.usb.org

More information about the WISHBONE SoC and a full specification can be found here.

The UTMI specification can be downloaded from here.

For further information, questions and general discussions related to the USB core, please visit the USB Mailing list. To subscribe to the USB mailing list go to the Mailing-Lists page and select usb from the pull down menu at the end of the page. Enter your email address and click "Do it!"

 

Status

 

Downloading

To get a tared and gziped snapshot from CVS click here, or go to the CVS info page.

The Specification is available here: usb_doc.pdf (about 280K)

 

Author / Maintainer

I have been doing ASIC design, verification and synthesis for over 15 years. I hope you find this cores useful. Please send me a note if you intend to use it !

Rudolf Usselmann
rudi@asics.ws_NOSPAM
www.asics.ws

Feel free to send me comments, suggestions and bug reports.

 

Change Log