Project Name: Reed-Solomon Decoder

Introduction

On January 21, 1959, Irving Reed and Gus Solomon submitted a paper to the Journal of the Society for Industrial and Applied Mathematics. In June of 1960 the paper was published : five pages under the rather unpretentius title "Polynomial Codes over Certain Finite Fields". This paper describe a new class of error-correcting codes that are now called Reed-Solomon codes.

Reed-Solomon codes are block-based error correcting codes with a wide range of applications in digital communications and storage. Reed-Solomon codes are used to correct errors in many systems including: 

• Storage devices (including tape, Compact Disk, DVD, barcodes, etc)
• Wireless or mobile communications (including cellular telephones, microwave links, etc) 
• Satellite communications 
• Digital television / DVB 
• High-speed modems such as ADSL, xDSL, etc.

Reed Solomon codes are a subset of BCH codes and are linear block codes. A Reed-Solomon code is specified as RS(n,k) with s-bit symbols.

This means that the encoder takes k data symbols of s bits each and adds parity symbols to make an n symbol codeword. There are n-k parity symbols of s bits each. A Reed-Solomon decoder can correct up to t symbols that contain errors in a codeword, where 2t = n-k.
 

Specifications

Decoder RS(31,19)

• Operates in a 5-bit Galois Field GF(2⁵)
• Code word Length (n) : 31 symbols
• Data Length (k) : 19 symbols
• Error Correction Capability (t) : 6 symbols
• Primitive Polynomial p(x) = x⁵ + x² + 1

Decoder RS(255,223)

• Operates in a 8-bit Galois Field GF(2⁸)
• Code word Length (n) : 255 symbols
• Data Length (k) : 223 symbols
• Error Correction Capability (t) : 16 symbols
• Primitive Polynomial p(x) = x⁸ + x⁷ + x² + x + 1

Description

RS(31,19)

Our RS(31,19) consist five primary subsystem, they are Input block, Power Sums Tower, Sugiyama Tower, Correction Tower, and Error Values Module.

• Input block keeps the received word from transmission channel. The word consist of thirty onge 5-bit-register and two multiplexer 31 to 1x5 bit that each of mutiplexer made by 3 multiplexer 8 to 1x5 bit, 1 multiplexer 7 to 1x5 bit, and 1 multipplexer 4 to 1x5 bit.
• Power Sums Tower block counts the syndrome values of the received word. 
• Sugiyama Tower block is used to find the error locator polynomial  and error evaluator polynomial. 
• Correction Tower block determines the roots of error locator polinomial and error value from those error locations. 
• Error Values Module block consist of 5 bit Comparator, Invers Multipliers GF(2⁵), and Multiplier GF(2⁵). 

RS(255,223)

Almost the same design, just bigger.

Current Status : 

• Still working on behavioral and structural of RS(31,19)
• Building design for RS(255,223)

Mantainers and Authors

REED SOLOMON development team 

Current members : Ibrahim Budiarjo, Yudha Pratomo, Erik P Kamal, Christanto Sahat, Sarwono Sutikno