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Re: [fpu] Architecture
I have some comments:
1. Double (64-bit) precission should be supported
2. 80 and 128 bit can be done by software with special instructions that can perform
the operation on two cycles based on local 64 regs while internally I use two 64
regs then it can be considered as any multicycle instruction. I think this approach
needs some help from the datapath and the instruction issue unit so may be we can
drop the 80 and 128 support for now until we can have larger regs size
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>Well execution units gets both operands (either from register file,
>sign-extended immediate or what ever - it is responsibility of the issue
>stage to deliver propoer operands to particular execution unit) and
>operation code (which operation must be carried out on operands). Pipeline
>stalling and other control operation over pipeline are carried out in
>datapath controller and are not part of execution units (so datapath
>controller takes care for multicycle FP instructions).
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but if you want to have versions of the CPU with or without the FPU you will need to
modify many blocks.
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I fully support this idea....In fact, issue unit has to just issue the FPU
inst and operands to FPU and do not even need to know whether they are
single or multi cycle ( I am sorry, don't have much idea about OR1K, assuming
there is no out of turn execution and CPU has to wait until FPU finishes
its execution). In our architecture here, FPU acknowledges to the issue
unit when it is going to finish the execution (in fact one clock b4 that, so
issue unit can continue w/o missing a cycle). That way, FPU could be roughly
independent of CPU.
One more advantage of above approach is....we can have one simple FPU (just
for basic operation mult div etc) and we can also have coprocessor which may
be optional....because FPU and cop can be treated the same way by issue unit...
( i mean issue the inst and operands and FPU/cop will acknowledge if the intsruc
tion is meant for them).
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do you mean that FPU has to decode all instructions? and so all exe units?
I assume that the FPU and cpu will act synchronosly and there will be no handshake
which is suitable for pipelines and morework on the datapath controller.
do you suggest a micro sequencer for the FPU control? that will carry all fpu
operations and be connected to the cpu datapath?
Jamil Khatib
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