RE: [pci] TOP.v to TOP.sch

[Nico Weling <eedniwe@eed.ericsson.se>]

Hi Matt,

>I am in exactly the same situation, I only know VHDL not Verilog.  Is there
>any way you could tell me how you have gotten as far as you have.  I am
>having trouble even getting the project put together.

Copy ise-openpci.npl (provided by Uwe) to /pci/apps/crt/syn/webpack/

Manually add all source files from
	/pci/apps/crt/rtl/verilog/
	/pci/rtl/verilog/
	expcept the TOP.v to the project
	
Copy pci_constants.v
     pci_user_constants.v
     bus_commands.v
     ssvga_defines.v  to /pci/apps/crt/syn/webpack/
     
Now the project should compile without errors.

>I am using a Spartan-II development board 

I'm using a selfmade PCI-board but the PCI part it is similar to the MEMEC 
Spartan-II development board. 

>...and I would also like to attach
>something simple to the WB bus so that I can see if I can make it work.

This I didn't succeed yet. As soon as something works I let you know.


Regards,

Nico.

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