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[pci] Fw: PCI IP core
----- Original Message -----
From: "Tadej" <tadej@opencores.org>
To: "Oliver Amft" <oam@gmx.net>
Sent: Friday, May 18, 2001 12:31 AM
Subject: Re: PCI IP core
> Hi, Oliver!
>
> I just updated the PCI web on opencores. It would be nice,
> if you can comment web page and also the last PCI spec
> revision.
> We (Miha and I) tried to explain how we thought about
> PCI core and its subparts.
>
> Any experiences, you can share, would be appreciated.
>
> Best regards, Tadej.
>
> ----- Original Message -----
> From: "Oliver Amft" <oam@gmx.net>
> To: <mihad@opencores.org>
> Cc: <tadej@opencores.org>
> Sent: Thursday, May 17, 2001 9:17 AM
> Subject: PCI IP core
>
>
> > Miha
> >
> > I've seen your second posting in comp.arch.fpga regarding the PCI core
> > development. As I'm quite interested in the open/free core development I
> > would like to contribute in VHDL/Verilog design and/or advisory.
> > Background: I've about 5 years of experience in VHDL design and 2 years
> > with PCI, including a soft-processor based PCI regression test
> > environment for an ASIC development, FPGA designs including a
> > proprietary PCI core (Xilinx) and PCB PCI bus design (FPGAs,
> > Processors). Currently I'm doing a lot of VHDL consulting and design
> > advisory. Apart from some lines I've never done Verilog so far (might
> > become some new challenge, if necessary).
> > In the meantime I took some secounds to skip through the spec...that's
> > all so far. Maybe you can provide me with some greater detail of the
> > project and your working areas.
> >
> > Cheers,
> >
> > Oliver
> >
> > --
> > GMX - Die Kommunikationsplattform im Internet.
> > http://www.gmx.net
> >
> >
>