SV: [pci] Re: [oc] Re: WISHBONE serial block transfer

[Stefan Bergström <stb@viking2001.se>]

I am working with the Altera core and I got some parts working now.

Have Fun
STB

-----Ursprungligt meddelande-----
Från:	Isa Servan Uzun [SMTP:uzun@bornova.ege.edu.tr]
Skickat:	den 26 april 2001 08:20
Till:	pci@opencores.org
Ämne:	Re: [pci] Re: [oc] Re: WISHBONE serial block transfer

Hi Jason,

Which PCI core did you purchase?
It is important for me because we've just purchased Altera' s PCI core and
I can' t cope with it.

Thanks.

----- Original Message ----- 
From: "Jason Silcox" <jsilcox@yahoo.com>
To: <pci@opencores.org>
Sent: Thursday, April 26, 2001 2:34 AM
Subject: [pci] Re: [oc] Re: WISHBONE serial block transfer


> 
> First time I've said anything here, so please forgive me if I
> fall on my face...
> 
> I've just finished working on a design with a PCI interface...
> We purchased a PCI core for use in the design and I was involved
> in connecting it to the internal blocks of the design...
> 
> Burst writes were easy to handle as a Target... Just buffer the
> data and don't accept a PCI read command until all data has been
> released...
> 
> Burst reads were a bit tricky, but if you really understand the
> PCI bus standard you'll see that a burst read and a single read
> are really no different....
> 
> Basically you have 2 situations
> (for this example Initiator refers to the PCI device asking for
>  the data, and Target refers to the PCI core...)
> 1) Initiator wants one DWORD... Operation is initiated and the
>    Initiator immediately indicated that this is the last byte
>    it needs by deasserting the FRAME PCI bus signal.  If the
>    Target doesn't abort the operation by asserting the STOP
>    PCI bus signal, it puts the requested DWORD on the bus and
>    asserts the TRDY PCI bus signal. The operation then completes.
> 
> 2) Initiator wants more than one DWORD...  The Initiator keeps
>    the IRDY and FRAME PCI bus signals asserted as long as it
>    needs more data (deasserting the IRDY signal to pause the
>    operation if necessary).  When the Target has a valid DWORD
>    it asserts the TRDY PCI bus signal until the Initiator has
>    asserted IRDY at the same time to acknowledge reception of
>    the DWORD.
> 
> The point is, if you don't have data immediately, it's OK...
> The Target has 16 PCI cycles to start the transfer and can
> issue a Target-Retry (Master ends current operation, but can
> retry later)...
> 
> What happens on the WB bus will effect the performance of
> the PCI bus, but doesn't have to "indicate" a block transfer,
> since block and single DWORD transfers are the same to PCI...
> 
> I guess I'm just making a point, not really answering the
> question asked...
> 
> Although, I think I'll look over the WB spec and do a bit of
> thinking...
> 
> Thanks for your time...
> ---
> Jason Silcox
> 
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