RE: [fpu] FPU operations

[Jamil Khatib <jamilkhatib75@yahoo.com>]

> 
> All the FPU has to provide, is status outputs. All
> the masking
> and dealing with the status/exceptions, is done by
> the CPU internally.
> 
> Here is a rough outline of the FPU IOs as I presume
> the CPU
> would want to see them:
> 
> INPUT	[31:0]	operand A
> INPUT [31:0]	operand B
> INPUT [3:0]		operation type (TBD, perhaps more bits
> ?)
> OUTPUT [31:0]	result
> OUTPUT		larger then ( A > B )
> OUTPUT		smaller then (A < B)
> OUTPUT		equal ( A == B )
> OUTPUT		unordered ( A == NAN | B == NAN )
> OUTPUT		overflow
> OUTPUT		underflow
> OUTPUT		SNAN
> OUTPUT		INE
> OUTPUT		INF (not sure we need this)

what do you mean by INF? Infinity ? if so we do not
need it.

you missed teh divide by zero exception


We need also an interface to rounding modes which
should be an input to the FPU if we want to support
more rounding modes. another alternative is to put as
part of teh operation.
Anyhow I suggest to have a register to store teh mode
to avoid having different instructions only one will
be needed that sets teh rounding mode

Regards
Jamil KHatib

> 
> Damjan, did I forget something ?
> 
> Regarding pipelining:
> I would suggest that all the basic functions (add,
> sub, mul and divide)
> take the same amount of cycles to execute. I think
> this will make it
> easier from the CPUs point of view.
> 
> Now, more complex operations (for example square
> root) might be variable
> length execution units, that might signal to the CPU
> when they are done.
> Damjan, can this be done with OR1K ? The CPU would
> have to monitor the
> completion and write the result back out of order.
> If another operation
> is trying to access the result before it is ready,
> the CPU would have to
> stall, or enter a trap. This could be avoided by
> having the compiler
> perform instruction sorting and scheduling. So that
> a instruction that
> is know to take two (or more) regular instruction
> cycles to execute, are
> not placed back to back. However, now you might need
> an additional write
> port for the FPU register file (which I assume is
> kept inside the OR1K,
> not the FPU).
> 
> Cheers,
> rudi
> 
> 
> >-----Original Message-----
> >From: owner-fpu@opencores.org
> [mailto:owner-fpu@opencores.org]On Behalf
> >Of Jamil Khatib
> >
> >
> >So I have to provide exception signals on the FPU
> >interface and the CPU core has to provide mask
> unmask
> >operation and generate interrupts but what about
> >rounding modes does the core need to provide the
> >signals
> >
> >Also compare results status register?
> >
> >I do not know if there are more registers to have
> >later
> >
> >Should I provide all these signals
> >
> >regards
> >Jamil
> 
>
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