[fpu] FPU spec

[Jamil Khatib <jamilkhatib75@yahoo.com>]

Hi,

I've finished the first preliminary release of the FPU
spec and design notes. Please give me some
constructive comments
The files are located under the FPU main page
http://www.opencores.org/cores/fpu/

The spec is "fpu_project.html" or "fpu_project.ps"
Main block diagram "BlockDiagram.ps"
Adder flow chart "add_flow.ps"
Decoder Flow chart "decode_flow.ps"
Comparator Flow chart "compare_flow.ps"

You can also find a summary of the IEEE-754 standard
at
www.geocities.com/SiliconValley/Pines/6639/docs/fp_summary.html


I'd like to suggest to represent NaN as 1 in the msb
of the fraction and all other bits as zeros. The
standard does not define the fraction bits of NaN. The
exponent should be all ones and the fraction should
not be all zeros. Some times my suggested
representation is called SNaN Signaling NaN, and I do
not know if we should support it in our design.

my suggested adder flow chart has unbalanced branches,
could you give me some suggestions?

I'll put some VHDL codes in the CVS in few days

Note: Please give me some constructive comments and
not ......

Regards
Jamil Khatib



__________________________________________________
Do You Yahoo!?
Get Yahoo! Mail – Free email you can access from anywhere!
http://mail.yahoo.com/