Re: [fpu] Architecture

["Guoqing Zhang" <gxz0233@hotmail.com>]

hi, guys:

Do you have matrials about 8087? I want to get more details about it's
80-bit FPU.appreciate!

Guoqing Zhang



>From: "Vladimir" <vladimir@fotocomp.fi>
>Reply-To: fpu@opencores.org
>To: <fpu@opencores.org>
>Subject: Re: [fpu] Architecture
>Date: Thu, 4 May 2000 11:12:40 +0300
>MIME-Version: 1.0
>Received: from [212.30.75.89] by hotmail.com (3.2) with ESMTP id 
>MHotMailBADA7ED00023D820F3CDD41E4B5960320; Thu May 04 01:24:52 2000
>Received: (from majordom@localhost)by iza.mr2.si (8.9.1/8.9.1) id 
>KAA01240for fpu-list; Thu, 4 May 2000 10:12:04 +0200
>Received: from fotocomp.fi (IDENT:root@fotocomp-pc.jsp.fi 
>[193.209.12.70])by iza.mr2.si (8.9.1/8.9.1) with ESMTP id KAA01237for 
><fpu@opencores.org>; Thu, 4 May 2000 10:11:56 +0200
>Received: from arc5 (arc5.fotocomp.fi [192.168.2.52])by fotocomp.fi 
>(8.9.3/8.9.3) with SMTP id LAA12705for <fpu@opencores.org>; Thu, 4 May 2000 
>11:11:35 +0300
>From owner-fpu@opencores.org Thu May 04 01:26:26 2000
>X-Authentication-Warning: iza.mr2.si: majordom set sender to 
>owner-fpu@opencores.org using -f
>Message-ID: <005901bfb5a0$840f4010$3402a8c0@fotocomp.fi>
>References: <Pine.LNX.3.96.1000423104305.32365B-100000@ic.vlsi.itb.ac.id> 
><390296D5.E668DD2E@yahoo.com> <009501bfadef$00d87d00$2201f9c2@gamma> 
><39068810.EB90FCA0@yahoo.com> <06da01bfb1e1$07df83f0$3b01f9c2@gamma> 
><390BF4B1.D753332@yahoo.com> <07b501bfb2b5$91c0f570$3b01f9c2@gamma>
>X-Priority: 3
>X-MSMail-Priority: Normal
>X-Mailer: Microsoft Outlook Express 5.00.2314.1300
>X-Mimeole: Produced By Microsoft MimeOLE V5.00.2314.1300
>Sender: owner-fpu@opencores.org
>Precedence: bulk
>
> > Do we really need 80 and 128 bit precision? I guess at least for a start
> > single and double precision would be enough. In fact I would put in our
> > first silicon test run (hopefully this will happen at the end of summer)
> > only single precision FPU since I think it is important to have small 
>die
> > (at least for the first silicon). Idea is to be able to "sell" this 
>first
> > implementation chips for a price of a hamburger. ;-)
>
>The IEEE 754 does not insist on implementing double precision but strongly
>recommends that an implementation should support the "extended precision"
>format corresponding to the widest basic. In case of 64-bit double format
>the extended has _at least_ 79 significant bits. For 32-bit single it 
>should
>have _at least_ 43. This policy is needed to support a sequence of
>continuous operations with a little bit higher precision before rounding
>them to the basic format. That is why x87s and later Intel FPUs keep the
>internal representation 80-bit wide. It is easy as long as you use a
>separate register space.
>
>As far as I could understand you want to use double precision because it
>fits well into 64-bit register file. Strictly speaking you may pretend that
>your implementation conforms to IEEE 754 implementing only the single basic
>precision and using double as its extension. You cannot claim to support 
>the
>double precision without implementing the extended format for it.
>
>Vladimir Ushakov
>

________________________________________________________________________
Get Your Private, Free E-mail from MSN Hotmail at http://www.hotmail.com