Re: [fpu] Architecture

[Usef Saiful-Ulum <usef@vlsi.itb.ac.id>]

Hi Jamil, sorry for belated response.

I would prefer a straight forward approach, FPU should accept insn from
instruction unit of CPU. In this regard, the FPU is the same level with
the integer unit. There are some considerations why I choose this
approach:

1. FPU should execute FP insn concurrently with other insns
2. From the programmer's point of view, the FPU and the CPU look if they
are integrated on a chip, so the FPU gives insns extension
3. It is the responsibility of the CPU to recognize whether it is an FP
insn or not, so the decode/dispatch unit of the insn unit can directly
dispatch the operands (and other field of the FP insn) to the appropriate
place (e.g. FPR, arithmetic unit, rename buffer,e tc)
4. We can share the load/store unit of the FPU with the Integer Unit.
5. We want a low latency access to FPU, so we can make the FPU as an
execution unit

In the implementation, we will need a reservation unit for arithmetic unit
to reduce stalls and rename buffers to avoid contention for a given FPR.

I'm somewhat busy within this week, so my resonse maybe late. But I'll try
to send some suggestions of the architecture soon.

rgrds,
Usef


On Thu, 20 Apr 2000, Jamil Khatib wrote:
> 
> May be it will be esier if we consider that the FPU will get ordered
> instructions and execute them and send back the results.
> 
> I have a suggestion, can we make the FPU as a memory mapped device and
> the CPU needs to write the operands in the correct address that defines
> the operation and reads back the result from a specific register.
> What do you think is it going to delay the CPU execution?