No Subject

[zhu.xiangyang@mail.zte.com.cn]

Hello everyone:
    I am a new comer to this mailinglist(so i have no any contribution to
opencore :( ).
Because i have been engaged in IC design only for a short time, there are some
question
puzzling me. I am using Verilog HDL. During my coding someone inspected my code
and told
me there are probably some problems in my code.
    My code is illustrated as follows:

 module(clk, reset, y, a, b, sel_a, sel_b);
   input clk, reset, a, b, sel_a, sel_b;
   output y;
   reg y;
   always@(posedge clk or negedge reset)
     begin
     if(reset)
       y <= 0;
      else
        begin
    //////////////
        if(sel_a)
          y <= a;
        if(sel_b)
          y <= b;
    /////////////
        end
     end
 endmodule

The inspector told me i should do as below:
 ////////////
     if(sel_b)
       y <= b;
     else if(sel_a)
       y <= a;
 ////////////
He said if i do as i like pre-synthesis simulation and post-synthesis
may be diffenent, because different synthesis tools may interpret it
differently. He demanded me to change my code. If i have to change my
code it will be a disaster, because i  have writen about 4,000 lines
of code using the same structer.

Must i change my code? Please help me.