Re: [oc] Programs in Xilinx Block RAM

[jesus@opencores.org]

> Unfortunately I don't have Xilinx Foundation Software :( 
> I am using WebPack & the CoreGen is not included in the WepPack 

I had the same problem so I wrote two small programs to generate the 
necessary files.
The source files can be dowloaded from my ax8 project in
http://www.opencores.org/cvsweb.shtml/ax8/sw/
The source files are hex2rom.cpp and xrom.cpp
Binaries compiled for win32 can be downloaded from:
http://www.e.kth.se/~e93_daw/vhdl/download/hex2rom_0221_Win32.zip

Example batch files that generates ROMs and compiles them together 
with a microcontroller can be found in:
http://www.opencores.org/cvsweb.shtml/ax8/syn/xilinx/run/

xrom generates VHDL files for Xilinx XST synthesis that can use block 
RAM or LUTs as ROMs or both (If you are low on one of them).
hex2rom accepts binary, motorola or intel input files and can generate 
configuration files for Xilinx XST synthesis or VHDL ROMs compatible with 
both simulation and Leonardo synthesis (Leonardo can synthesize ROMs 
to block RAM from portable code).
If you prefer verilog it shouldn't be to hard to modify xrom to
generate verilog or to port the generated VHDL ROM entity to verilog
by hand and just use hex2rom to generate configuration files.

Regards,
 Daniel Wallner
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