Re: [oc] Low power design

[Billditt@aol.com]

Low power design is what I call hierarchical.
At low ends, it consists of simple things like turning
off I/O drivers till they are needed (you hit that)
     Then you move up
to next level, which basically means turning off clocks
to logic en mass. For instance, turn off clocks to TX
portion when RX is being used, etc. This is easy to do
but can be tough on timing analysis, and not necessarily
easy inside an FPGA.
    Another level up is turning off clocks selectively inside a
function during operations , turning them back on just in time
for use (then off again). For instance, as data moves
thru a pipeline, clocks would be turned on in presently
used stage (x) and for the next to be used stage (x+1). Once data
has been moved on, the last stage is shut down (x), while x+1, x+2
are clocked. Kind oflike a ripple. This takes sophisticated control, 
both locally and  often from a power management unit.

    Finally, shutting down sections of logic. Something like a 
memory controller suspendig operation, putting SDRAM into
self refresh, and actually cutting power to everything except the
clock enable line (keep SDRAM in self refresh). 
This is really involved, you probably need a 
circuit designer, etc. Usually domain of the big boys.

    So, its a matter of deciding what level of savings you need.
You pay more in control complexity, gated clocks, etc. as you gain
power savings. Usually, you dont go in for any more complexity than
you absolutely need to realize power savings. Your first question should
be, what is my power budget. From that, you can figure out roughly what
is power savings (I/O, core logic, etc). Also, if you are going to do
an ASIC, look for low power libraries.
    
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